The present invention relates to a method of photoresist or photolithographic etching utilized in the integrated circuit art. More particularly, it relates to a method of etching using positive photoresist masking which makes it possible to embed metallurgy levels within the body of, i.e., below the surface of an insulative layer to thereby produce integrated circuits with multilevel metallurgy in which deviations from planarity are minimized.
In the construction of thin film integrated semiconductor circuits wherein a plurality of passivating or insulating films or layers are formed between a plurality of raised conductive line patterns, e.g., metallization patterns, the insulative layers follow the contours of the underlying metallization patterns, i.e., the insulative layers will have raised portions or elevations corresponding to those in the underlying metallization patterns. The integrated circuit art has long recognized that in multilayered structures, the cumulative effect of several levels of raised metallization on the final insulative layer could be very pronounced and undesirable. Consequently, the art is constantly seeking ways to minimize such elevations and to approach planarity.
The attempts in the prior art to minimize the cumulative or "skyscraper" effect in the case of multilevel metallurgy have been many and varied. Some approaches toward the solution of this "skyscraper" effect involve resputtering to eliminate the elevations, as described in U.S. Pat. No. 3,868,723, or by selective etching involving a reflowed photoresist material as described in copending application, Ser. No. 480,086, B. Feng, filed June 17, 1974, U.S. Pat. No. 3,976,524.
The method of the present invention provides a simple approach to the problem of achieving planarization in multilevel metallurgy integrated circuit structures.